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(preliminary) pl610 - 01 1.8v to 3 .3v , 1mhz to 130mhz xo ic 47745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 www.phaselink.com rev 4/2 /07 page 1 1 2 3 4 5 6 oe ^, pdb ^, clk 1 gnd xin , fin vdd xout clk 0 dfn - 6 l ( 2 . 0 mmx 1 . 3 mmx 0 . 6 mm ) sot 23 - 6 l ( 3 . 0 mmx 3 . 0 mmx 1 . 35 mm ) xin , fin gnd xout vdd clk 0 oe ^, pdb ^, clk 1 1 4 5 6 3 2 features ? w ide frequency coverage, programmable , a dvanced oscillator design. ? programmable ?odd/even? divider up to 63 ? d irect oscillation operation with optional programmable features: o output drive strength (4, 8, or 16ma) o 6 - bit odd/even output divider ? input frequency: o fundamental c rystal: 5mhz to 1 3 0mhz o reference clock : 1 mhz to 1 3 0mhz ? supports cmos or sine wave input clock ? output f requency: 20khz to 1 3 0mhz ? very low jitter and phase noise ? low current consumption ? single 1.8v, 2.5v, or 3.3v 10% power supply ? operating temperature range from - 40 ? c to 85 ? c description the pl610 is a high performance general purpose oscillator ic for outputs up to 130mhz . desi gned to fit in a small 2 x 1.3 mm dfn or 3 x 3mm sot23 package , the pl610 offers the best phas e noise and jitter performance and lowest power consumption of any comparable ic. in addition, there is a ?6? bit optional programmable odd/even divider (default= ? 1), and ?3? programmable output drive strengths (4ma, 8ma (default), 16ma) to choose from. the full feature set of the pl610 makes it the most versatile xo for any application. p ackage pin configuration block diagram
(preliminary) pl610 - 01 1.8v to 3 .3v , 1mhz to 130mhz xo ic 47745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 www.phaselink.com rev 4/2 /07 page 2 key programming parameters (optional) clk [0:1] output frequency output drive strength programmable input/output f out = f ref / p * ( *: p is an odd/even divider) where p = 6 bit clk0 = f ref , f ref /2 or f ref / p clk1 = f ref , f ref /2 or clk0 three optional drive st rengths to choose from: ? low: 4ma ? std: 8ma (default) ? high: 16ma one output pin can be configured as: ? oe - input ? pdb - input ? clk1 ? output package pin and die pad assignment pin assignment name dfn - 6l sot 23 - 6l type description xin, fin 1 3 i cr ystal or reference clock input pin oe, pdb, clk1 2 1 i/o this programmable i/o pin can be configured as an output enable (oe) input, power down input (pdb) input or clk1 clock output . this pin has an internal 60k ? p u l l u p r e s i s t o r for oe and 10m ? p u l l up resistor for pdb . state oe pdb 0 tri - state clk power down mode 1 (default) normal mode normal mode gnd 3 2 p gnd connection clk0 4 6 o programmable clock output vdd 5 5 p vdd connection crystal output pin xout 6 4 o do not connect (dnc ) w hen fin is present
(preliminary) pl610 - 01 1.8v to 3 .3v , 1mhz to 130mhz xo ic 47745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 www.phaselink.com rev 4/2 /07 page 3 functional description pl610 - 01 is a highly featured, very flexible, advanced xo design for high performance, low - power, small form - factor applications. the pl610 - 01 accepts a fundamental input crystal of 5 mhz to 130 mhz or a refere nce clock input of 1mhz to 1 3 0mhz and is capable of producing two outputs up to 1 3 0mhz. this flexible design allows the pl610 - 01 to deliver any frequency, fref (crystal or ref clk) frequency , fref / 2 or fref / p to clk0 and/or clk1. some of the design f eatures of the pl610 - 01 are mentioned below: clock output (clk0) clk0 is the main clock output. the output from clk0 can be fref (crystal or ref clk), f ref/ 2 or fref/p output. the output drive level can be programmed to low drive (4ma), standard drive (8ma) or high drive (16ma). programmable i/o (oe/pdb /clk1) the pl610 - 01 provides one programmable i/o pin which can be configured as one of the following functions: output enable (oe) the output enable feature allows the user to enable and disable the clo ck output(s) by toggling the oe pin. the oe pin incorporates a 60k ? p u l l u p resistor giving a default condition of logic ?1?. power - down control (pdb) the power down (pdb) feature allows the user to put the pl610 - 01 into ?sleep mode?. when activated (lo gic ?0?), pdb ?disables the pll, the oscillator circuitry, counters, and all other active circuitry. in power down mode the ic consumes <10a of power. the pdb pin incorporates a 10m ? pull up resistor giving a default condition of logic ?1?. clock output (clk1) the clk1 feature allows the pl610 - 01 to have an additional clock output programmed to one of the following: fref - reference ( crystal or ref clk) frequency fref / 2 clk0
(preliminary) pl610 - 01 1.8v to 3 .3v , 1mhz to 130mhz xo ic 47745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 www.phaselink.com rev 4/2 /07 page 4 layout recommendation s the following guidelines are to assist you wi th a performance optimized pcb design: signal integrity and termination considerations - keep traces short! - trace = inductor. with a capacitive load this equals ringing! - long trace = transmission line. without proper termination this will cause r eflections (looks like ringing) . - design long traces as ?striplines? or ?microstrips? with defined impedance. - match trace at one side to avoid reflections bouncing back and forth. decoupling and power supply considerations - place decoupling capacitors as close as possible to the vdd pin(s) to limit noise from the power supply - multiple vdd pins should be decoupled separately for best performance. - addition of a ferrite bead in series with vdd can help prevent noise from other board sources - value of decoupling capacitor is frequency dependant. typical values to use are 0.1 ? f for designs using crystals < 50mhz and 0.01 ? f for designs using crystals > 50mhz. series and parallel capacitors used to fine tune the crystal load to the circuit load . ? series capacitor , used to lower circuit load to match crystal load . raises frequency offset . this can be eliminated by using a crystal with a cload of equal or greater value than the oscillator . ? parallel capacitors , used to raise the circuit load to match the crystal load . lowers frequency offset . crystal xin 1 8 xout cpt cpt cst
(preliminary) pl610 - 01 1.8v to 3 .3v , 1mhz to 130mhz xo ic 47745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 www.phaselink.com rev 4/2 /07 page 5 electrical specifications absolut e maximum ratings parameters symbol min. max. units supply voltage range v dd - 0.5 4.6 v input voltage range v i - 0.5 v dd +0.5 v output voltage range v o - 0.5 v dd +0.5 v storage temperature t s - 65 150 ? c ambient operating temperature * - 40 85 ? c exposure of the device under conditions beyond the limits specified by maximum ratings for extended periods may cause permanent damage to the device and affect product reliability. these conditions represent a stress rating only, and functional operations of the d evice at these or any other co n ditions above the operational limits noted in this specification is not implied . *operating temperature is guaranteed by design. parts are tested to commercial grade only. ac specifications parameters conditions min. ty p. max. units crystal input frequency fundamental crystal 5 130 mhz @ v dd =3.3v @ v dd =2.5v input (fin) frequency @ v dd =1.8v 1 130 mhz input (fin) signal amplitude internally ac coupled (high frequency) 0.9 v dd vpp input (fin) signal amplitude internally ac coupled (low frequency) 3.3v < 50mhz, 2.5v < 40mhz, 1.8v < 15mhz 0.1 v dd vpp output frequency @ vdd= 1.8v - 3.3v 20khz 130 mhz vdd sensitivity frequency vs. vdd+/ - 10% - 2 2 ppm output rise time (see mtc - 1) 15pf load, 10/90%vdd, h igh drive, 3.3v 1 1.2 ns output fall time (see mtc - 1) 15pf load, 90/10%vdd, high drive, 3.3v 1 1.2 ns duty cycle (see mtc - 1) 45 50 55 %
(preliminary) pl610 - 01 1.8v to 3 .3v , 1mhz to 130mhz xo ic 47745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 www.phaselink.com rev 4/2 /07 page 6 dc specifications parameters symbol conditions min typ max units @vdd=3.3v, 25mhz, load=15pf 3.4 ma @vdd=2.5v, 25mhz, load=10pf 2.1 ma @vdd=1.8v, 25mhz, load=5pf 0.9 ma supply current, dynamic, with loaded cmos output i dd @vdd=1.8v, 2.0mhz, load=5pf 0.65 ma operating voltage v dd 1.62 3.63 v output low voltage v ol i ol = +4ma standard drive 0 .4 v output high voltage v oh i oh = - 4ma standard drive v dd ? 0.4 v output current, low drive (see mct - 2) i old v ol = 0.4v, v oh = 2.4v 4 ma output current, standard drive (see mct - 2) i osd v ol = 0.4v, v oh = 2.4v 8 ma output current, high drive (se e mct - 2) i ohd v ol = 0.4v, v oh = 2.4v 16 ma crystal specifications (5mhz - 60mhz) parameters symbol min. typ. max. units fundamental crystal resonator frequency f xin 5 60 mhz crystal loading ra t ing (the ic can be programmed for any value in this range. ) c l (xtal) 8 12 pf maximum sustainable drive level 100 ? w operating drive level 25 ? w ? crystal shunt capacitance c0 3 pf ? effective series resistance, fundamental, 5 - 60mhz (see mtc - 1) esr 50 ? ?
(preliminary) pl610 - 01 1.8v to 3 .3v , 1mhz to 130mhz xo ic 47745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 www.phaselink.com rev 4/2 /07 page 7 crystal specifications (60mhz - 130mhz) parameters symbol min. typ. max. units fundamental crystal reson ator frequency f xin 60 130 mhz crystal loading ra t ing (the ic can be programmed for any value in this range.) c l (xtal) 5 8 pf maximum sustainable drive level 100 ? w operating drive level 25 ? w ? crystal shunt capacitance c0 2.5 pf ? effective s eries resistance, fundamental, 60 - 130mhz (see mtc - 1) esr 30 ? ?
(preliminary) pl610 - 01 1.8v to 3 .3v , 1mhz to 130mhz xo ic 47745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 www.phaselink.com rev 4/2 /07 page 8 measurement test circuits (mtc) mtc - 1: rise time, fall time, duty cycle, vol, voh, i dd , power down current, output enable/disable mtc - 2: output drive cu rrent and output impedance mtc - 3: jitter and phase noise mtc - 4: negative resistance xout xin oe^ probe fet clk vdd gnd 0.1f 0.1f v r xout oe^ gnd 0.1f xin clk vdd 0.1f xin oe^ xout clk gnd vdd 0.1f network analyzer xin vdd xout gnd clk oe^ fet probe cl a 0.1f
(preliminary) pl610 - 01 1.8v to 3 .3v , 1mhz to 130mhz xo ic 47745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 www.phaselink.com rev 4/2 /07 page 9 waveform switching characteristics rise and fall time s: duty cycle: voh, vol: tr tf 10%vdd 90%vdd 50%vdd tw t duty cycle = 100% tw t gnd vdd voh vol
(preliminary) pl610 - 01 1.8v to 3 .3v , 1mhz to 130mhz xo ic 47745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 www.phaselink.com rev 4/2 /07 page 10 package drawings ( green package compliant) min. max. a 0.5 0.6 a1 0 0.05 a3 b 0.15 0.25 e d 1.25 1.35 e 1.95 2.05 d1 0.75 0.85 e1 0.95 1.05 l 0.2 0.3 symbol dimension (mm) 0.40bsc 0.152 ref recommended land pattern ( mm ) 2 . 362 1 . 905 0 . 915 0 . 05 1 . 473 0 . 95 0 . 482 0 . 050 3 . 785 0 . 50 e h d pin 1 dot c l a 2 a 1 e b a min max a 1.05 1.45 a1 0.05 0.15 a2 1.00 1.30 b 0.35 0.50 c d 2.80 3.00 e 1.50 1.70 h 2.60 3.00 l 0.35 0.55 e symbol dimension (mm) 0.127 typical 0.95 typical
(preliminary) pl610 - 01 1.8v to 3 .3v , 1mhz to 130mhz xo ic 47745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 www.phaselink.com rev 4/2 /07 page 11 ordering information ( green package) for part ordering, please contact our sales department: 47745 fremont blvd., fremont, ca 94538, usa tel: (510) 492 - 0990 fax: (510) 492 - 0991 part number the ord er number for this device is a combination of the following: part number, package type and operating temperature range pl6 10 - 01 - xx x x x x part /order number marking ? package option pl610 - 01 - xxx g c - r xxx 6 - pin dfn (tape and reel) pl6 10 - 01 - xxx tc - r e1xxx 6 - pin sot - 23 (tape and reel) ? note: ?xxx? designates marking identifier that could be independent of the part number. phaselink corporation, reserves the right to make changes in i ts products or specifications, or both at any time without notice. the information fu r nished by phaselink is believed to be accurate and reliable. however, phaselink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. life support policy : phaselink?s products are not authorized for use as critical components in life support devices or systems without the e x press written approval of the president of phaselink corporation. solder reflow profile available at www.phaselink.com/qa/solderinggreen.pdf part number temperature c =commercial i=industrial package type t=sot 23 - 6l g=dfn - 6l 3 digit id code * (will be assigned at programming time) n one= tube r=t ape and reel

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